The present invention relates to phase locked loops (PLLs) and more particularly to “self-biased” PLLs with dynamic parameters that are substantially independent of a PLL divider ratio. The term “self-biased PLL” is used (see the Maneatis paper cited below) to describe a PLL in which the bias current of the charge pump is self-regulating and adapts for other circuit tolerances.
FIG. 1 shows a block diagram of a general form of one kind of PLL, that general form being known in the art. The circuit of FIG. 1 comprises a phase comparator 1, a charge pump 2, a loop filter 3, a voltage controlled oscillator (VCO) 4 and a frequency divider 5 and has an input 6 and an output 7. The phase comparator 1 has two inputs and two outputs. The charge pump 2 has two inputs and an output. Each one of the loop filter 3, the VCO 4 and the frequency divider 5 have an input and an output. The first input of the phase comparator 1 is coupled to the input 6 of the PLL and the second input of the phase comparator is coupled to the output of the frequency divider 5. First and second of the outputs of the phase comparator 1 are respectively coupled to first and second of the inputs of the charge pump 2, the output of the charge pump 2 is coupled to the input of the loop filter 3 and the output of the loop filter 3 is coupled to the input of the VCO 4. The input and output of the loop filter 3 are coupled together. The output of the VCO 4 is coupled to both the output 7 of the PLL and the input of the frequency divider 5. The VCO 4 might alternatively have two differential outputs, or more than two outputs providing a multi-phase output.
The frequency of the signal at the output 7 of the PLL is N times the frequency of the signal at the input 6 of the PLL. N is the divider ratio of the frequency divider 5 so that the frequency at each of the inputs to the phase comparator 1 should be the same. The outputs of the phase comparator 1 are dependent on the phase difference between the two inputs of the phase comparator, one of those outputs indicating that the PLL output 7 is advanced relative to the input, the other indicating that that output is retarded. The outputs of the phase comparator 1 cause the charge pump to increase or decrease respectively the current input to the loop filter 3, and hence the voltage supplied to the VCO 4, accordingly. The phase comparator 1 could be replaced with a frequency comparator or with a combined frequency and phase comparator. The PLL is arranged so that when the frequency at the output of the frequency divider 5 is higher than the frequency at the PLL input 6, the output of the charge pump 2 is such that the frequency at the output 7 of the PLL is reduced and when the frequency at the output of the frequency divider 5 is lower than the frequency at the PLL input 6 the output of the charge pump 2 is such that the frequency at the output 7 of the PLL is increased. Thus the PLL has a feedback loop that forces the frequency at the output of the frequency divider towards the frequency at the input 6. With suitable conditions, the frequency at the output of the PLL will lock to the frequency at the input of the PLL and the output will follow any changes in the frequency or phase of the input to the PLL. The inputs of the phase comparator may have the same phase when in lock or may have some other phase relationship, such as being 90° out of phase.
The loop filter 3 is a low pass filter that prevents the output of the PLL from being unstable. The frequency response of the low pass filter is essentially a balance between ensuring that the cut-off frequency is high enough to enable the PLL to track input frequency variations and power supply noise but low enough to smooth over noise in the input signal to ensure that the PLL is stable. The design of the loop filter 3 will depend, amongst other things, on the application but a typical circuit that is used is shown in FIG. 2. FIG. 2 shows a resistor 8 with a first terminal connected to a first terminal of the loop filter and a second terminal connected to a first terminal of a first capacitor 9, the first capacitor having a second terminal connected to a second terminal of the loop filter. The filter also has a second capacitor 10 with first and second terminals connected to the first and second terminals of the loop filter respectively. The first terminal of the loop filter 3 is connected to both the output of the charge pump 2 and the input of the VCO 4 and the second terminal of the loop filter is connected to ground.
Two dynamic parameters of the PLL of FIG. 1 are a damping factor z and a bandwidth to compare frequency ratio ω3/ωref. The damping factor is a measure of the time it takes the circuit to return to a near ideal position after being disturbed. With a damping factor of 1, the PLL is critically damped, with a damping factor greater or less than 1, the PLL is over- or under-damped respectively. ω3 is the 3 dB frequency of the PLL, that is the frequency at which the open loop phase response of the PLL is 1/√2 of its maximum. ωref is the compare rate of the PLL that is the frequency of operation of the phase comparator (i.e. the frequency of the input signal at terminal 6).
The formulae for z and ω3/ωref are known in the art (see, for example, Chapter 2 of Gardner “Phaselock Techniques”, John Wiley & Sons, Second edition) and are:       z    =                  1        2            ⁢                                                  k              D                        ⁢                          I              P                        ⁢                          R              2                        ⁢            C                                2            ⁢            π            ⁢                                                   ⁢            N                                                  ω        3                    ω        ref              =                            k          D                ⁢                  I          P                ⁢        R                    2        ⁢        π        ⁢                                   ⁢        N        ⁢                                   ⁢                  ω          ref                    wherein kD is a gain (radians/volt-second) of the VCO, Ip is the output current of the charge pump, R and C are the resistance and capacitance of the resistor 8 and the first capacitor 9 respectively in the loop filter and N is the frequency divider ratio.
The bandwidth to compare frequency ratio ω3/ωref is dependent on the PLL compare frequency itself and so any desired numerical value for ω3/ωref should preferably be satisfied for all values of ωref.
One measure of the performance of a PLL is the jitter that is seen at the output. Jitter is the deviation from the required edge position that is seen at the output of the PLL. Low-jitter PLLs result from optimising the dynamic parameters of PLLs. Two problems that have been identified in the optimisation are (1) the variation of component values, and therefore the dynamic parameters of the PLL, as a result of manufacturing tolerances in those components, and (2) the use of selectable frequency dividers so that the output can be at a selected multiple of the input frequency, when the dynamic parameters are usually optimised at one or more operating frequencies but not at others.
The bandwidth to compare frequency ratio ω3/ωref is dependent on the value of R in the loop filter 3 and the divider ratio N. The damping factor z is dependent on the values of R and C in the loop filter 3 and the divider ratio N. Thus both the bandwidth to compare frequency ratio and the damping factor are subject to both of the problems identified above.
The dynamic parameters z and ω3/ωref can be made substantially independent of the frequency divider ratio N using the technique disclosed in “A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability” (IEEE Journal of Solid-State Circuits, Vol. 34, No. 12, pp. 1951 to 1960) (Larsson). That article suggests setting the charge pump current to be proportional to the divider ratio N, so that:Ip=N.Ibias where Ibias is a constant current provided by a bias circuit. Thus the formulae for z and ω3/ωref above are reduced to:       z    =                  1        2            ⁢                                                  k              D                        ⁢                          I              bias                        ⁢                          R              2                        ⁢            C                                              2              ⁢              π                        ⁢                                                                       and                    ω        3                    ω        ref              =                            k          D                ⁢                  I          bias                ⁢        R                    2        ⁢        π        ⁢                                   ⁢                  ω          ref                    
The dependence of both the damping factor z and the bandwidth to compare frequency ratio ω3/ωref on the manufacturing tolerances of the components in the loop filter 3 is unaffected, as is the dependence of the bandwidth to compare frequency ratio on the compare rate ωref.
The variation of component values as a result of manufacturing tolerances affecting the value of z and ω3/ωref can be substantially reduced (but not eliminated) by the use of “self-biased” PLLs as in “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques” (IEEE Journal of Solid-State Circuits, Vol. 31, No. 11 pages 1723 to 1732) (Maneatis). In that paper, a “self-biased” PLL is disclosed in which R is made inversely proportional to the square root of a bias current, which is again termed Ibias, Ip is made proportional to Ibias and the output frequency is made proportional to the square root of Ibias. Thus:       z    =                  1        2            ⁢                                                  k              D                        ⁢                          a              2                        ⁢            bC                                              2              ⁢              π              ⁢                                                           ⁢              N                        ⁢                                                                       and                    ω        3                    ω        ref              =                            k          D                ⁢        ab                    2        ⁢        π        ⁢                                   ⁢        d              where            R      =              a                              I            bias                                ;                  I        P            =              b        ·                  I          bias                      ;                  and        ⁢                                   ⁢                  ω          out                    =              d        ⁢                              I            bias                          ⁢                                   ⁢                  (                      =                          N              ·                              ω                ref                                              )                    a, b and d being constants, but not necessarily independent of each other. Note that here Ibias is not constant in all circumstances but will vary with the output frequency of the circuit, which it controls, if for example the input reference frequency changes.
As discussed in Maneatis, a resistor with a resistance inversely proportional to the square root of the bias current can be obtained by using a MOSFET as an active resistor. For example, by connecting the gate of an MOS transistor to the drain of that transistor and applying a current to the drain of that transistor, the resistance between the source and the drain of the device is approximately inversely proportional to the square root of the current supplied to the drain.
The frequency at the output of a typical VCO is set by the value of an RC time constant in which the value of R is set using an active resistor as described above. Thus the frequency of oscillation (proportional to 1/RC) is made proportional to the square root of a bias current applied to that active resistor, as required by the formula above. The slope of the output frequency against Ibias graph gives the constant d.
It can be seen from the equations above that the self-biased PLL substantially reduces the effect of the first problem identified above (i.e. the variation of component values due to manufacturing tolerances) since the formula for ω3/ωref is independent of such tolerances and the damping factor z is dependent on the square root of the loop filter capacitance rather than on the loop filter resistance and the square root of the loop filter capacitance. Another significant advantage of the self-biased PLL is that ω3/ωref is not dependent on the PLL compare rate ωref.
However, for the self-biased PLL described in the Maneatis paper, the damping factor z is once again dependent on the frequency divider ratio N. The inventor has noted that this can be solved ifIp=N.b.Ibias but this makes ω3/ωref dependent upon N.
Thus whilst attempts have been made to solve the two problems associated with low-jitter PLLs identified above, namely the variation of component values, and therefore the dynamic parameters of the PLL, as a result of manufacturing tolerances in the components and the optimisation of dynamic parameters at some operating frequencies but not at others in phase locked loops with selectable frequency dividers, there remains a need for a phase locked loop with a selectable frequency divider that has a damping factor z and a bandwidth to compare frequency ratio ω3/ωref that are both substantially independent of the frequency divider ratio N, and for which ω3/ωref is independent of the compare frequency ωref.